1. Field of the Invention
The present invention relates to a highly integrated memory device having a stack capacitor structure in which a transistor and a capacitor included in each cell of the memory device are coupled to each other by a polysilicon contact plug in order to achieve an increase in the cell integration degree of the memory device, and more particularly to a stack capacitor in such a memory device, wherein a capacitor has a diffusion barrier capable of inhibiting an oxidation of the polysilicon contact plug while preventing an increase in contact resistance resulting from a reaction of the polysilicon of the contact plug with a lower electrode.
2. Description of the Prior Art
Referring to FIG. 1, there is a sectional view schematically illustrating a simple stack capacitor used in a conventional DRAM device.
As shown in FIG. 1, a lower insulating layer 13, which has storage electrode contact holes 15, is formed over a semiconductor substrate 11. Polysilicon is buried in the contact holes 15, thereby forming contact plugs 17.
Thereafter, a diffusion barrier layer 19 and a lower electrode layer for forming lower electrodes 21 are sequentially formed to desired thicknesses over the entire upper surface of the resulting structure.
The lower electrode layer and diffusion barrier layer 19 are then patterned in accordance with an etch process using a storage electrode mask (not shown), thereby forming diffusion barriers 19 and lower electrodes 21.
Over the entire upper surface of the resulting structure, a dielectric film 23 and a plate electrode layer for forming plate electrodes 25 as upper electrodes are then formed. Thus, stack capacitors are fabricated.
The stack capacitors are electrically connected to transistors formed on the semiconductor substrate 11 via the contact plugs 17, respectively.
The dielectric film 23 is made of a paraelectric or ferroelectric substance exhibiting a very high dielectric constant. Such a paraelectric or ferroelectric substance may be SrTiO.sub.3 (ST), (Ba.sub.x, Sr.sub.1-x)TiO.sub.3 (BST), Pb(Zr.sub.x, Ti.sub.1-x)O.sub.3 (PZT), or (Pb.sub.1-y, Lay) (Zr.sub.x Ti.sub.1-x)O.sub.3 (PLZT)
Typically, such a high-dielectric thin film should be deposited or annealed in an oxygen atmosphere maintained at a high temperature of 500 to 800.degree. C. so that it exhibits a desired dielectric constant and leakage current characteristics.
For the material of electrodes used in simple stack capacitors including dielectric films exhibiting a high electric constant, accordingly, a metal such as Pt, Ir or Ru or a conductive oxide such as IrO.sub.2 or RuO.sub.2 is typically used which exhibits a superior electrical conductivity and superior thermal resistance and anti-oxidation characteristics is typically used.
However, since the above-mentioned high-dielectric thin film made of, for example, ST, BST, PZT or PLZT is deposited in an oxygen atmosphere at a high temperature, oxygen may be easily diffused through the lower electrodes of the capacitors, so that it may react with the polysilicon of the contact plugs. As a result, an insulating layer such as a silicon oxide film may be formed at the interface of the polysilicon with the lower electrodes. That is, there is a problem in that an undesirable electrical insulation is established.
Meanwhile, Si may also be diffused into the lower electrodes. Such a diffusion of Si may result in a degradation in the physical properties of the deposited high-dielectric thin film.
Furthermore, when the material of the lower electrodes of the capacitors come into direct contact with the polysilicon, a reaction between these two materials may occur at a high temperature of 200.degree. C. or more, thereby producing PtSi exhibiting Schottky barrier characteristics. This results in a degradation in CMOS characteristics.
In order to inhibit an oxidizing diffusion of oxygen and Si atoms while preventing Si from coming into direct contact with the lower electrodes, a diffusion barrier layer is typically disposed between the lower electrodes of the stack capacitors and the Si layer.
In a highly integrated DRAM, such a diffusion barrier layer is mainly made of TiN having a resistivity while exhibiting superior diffusion barrier characteristics at a temperature of 600.degree. C. or less.
However, TiN loses its diffusion barrier effect to oxygen and Si in an oxygen atmosphere maintained at a high temperature of more than 600.degree. C. For this reason, TiN serves to greatly limit processing conditions including the deposition temperature of the high-dielectric thin film and the temperature of a subsequent thermal treatment.